The semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs. As this progression takes place, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as fin-like field effect transistor (finFET) device. A typical finFET device is fabricated with a thin “fin” (or fin-like structure) extending from a substrate. The fin usually includes silicon and forms the body of the transistor device. The channel of the transistor is formed in this vertically-extending fin. A gate is provided over (e.g., wrapping) the fin. This type of gate allows greater control of the channel. However, there has been a desire to have even greater control over the gate. Methods of performing such control include using gate-all-around and/or omega or quasi-surround architecture. However, fabrication of GAA structures faces substantial challenges. Similarly, quasi-surround architecture has processing challenges includes those introduced by their formation on a silicon-on-insulator (SOI) substrates.
Therefore, while existing methods of fabricating gate structures having improved control are adequate for some purposes, additional improvements may be desired.